The present disclosure relates in general to the field of integrated circuits. More specifically, the present disclosure relates to systems and methodologies for the testing of integrated circuit devices.
There is an increased desire for manufacturers, developers, and test organization to effectively test, characterize, and diagnose an integrated circuit (IC) more completely and at the lowest possible cost. One method of testing and characterizing is to use the Shmoo plot tool—a graphical representation of an IC's ability to operate properly in response to various combinations of values of various operating parameters. For example, one might repeatedly test an IC using different combinations of supply voltage and frequency to determine if the IC operates properly at those combinations and parameter ranges. This is typically mapped on a Shmoo plot. For example, the voltage can be on one axis of a scatter plot and the frequency can be on the other axis of the scatter plot. A test of the IC is done at each combination of voltage and frequency and the pass/fail status can be indicated on the shmoo plot.
A difficulty becomes evident when dealing with larger ICs such as VLSI chips known as systems on a chip (SOC) or complex multi-core processors with millions or even billions of transistors and heterogeneous circuits such as combinational logic, various types of memory, analog, and wireless RF. In such devices, the ability to adjust critical operating parameters, reconfigure the chip into separate regions, alter the data paths, and change test operations, might also be internal to the chip as an integral part of the chip design (in contrast to more traditional methods of controlling things like voltage, frequency, and chip test modes which can be controlled outside the IC). Strict external and limited internal test controls are not conducive to complex testing methodologies such as chip self-test and testing at application speeds and environmental conditions in various chip configurations.